The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced device scaling in which IC geometry size, such as decreasing feature size and pitch, is reduced. However, decreasing feature size and pitch can lead to collapse of photoresist features used in the manufacture of ICs.
Along with decreasing geometry size, ICs have increased in complexity. Dual-damascene interconnect features include planarized interconnect structures and multiple interconnect layers increasing the complexity of device integration. Low-dielectric constant (low-k) dielectric materials are being used in conjunction with copper dual-damascene interconnect features. Some low-k dielectric materials are porous, and it is difficult to adequately control the etch process, particularly in the dual-damascene structure and manufacturing processes.
There is a need for improved processes, materials, and structures in the removal of layer and materials to manufacture advanced ICs with decreasing geometry size and with increased complexity.